# set_operating_conditions 5_slow_900mv_-40c

#Входные клоки
create_clock -name inclk0 -period 50.000 -waveform {0 25} [get_ports {inclk0}]
create_clock -period "150 MHz" -name {SATA_refclk} {SATA_refclk}
# create_clock -name ref_clk -period 10.000 -waveform {0 5.0} [get_ports {ref_clk}]
# create_clock -period "106.25 MHz" -name {CLK_106_25_MHz} {CLK_106_25_MHz}
# create_clock -period "106.25 MHz" -name {CLK2_106_25_MHz} {CLK2_106_25_MHz}

derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

#описание клоков SATA
create_generated_clock -name SATA_CLK -source [get_pins {inst2|ip_sata_0|block_sata_core_gxb_inst1|inst2|ALTGX_SATA_alt4gxb_component|transmit_pcs0|clkout}] -divide_by 2 [get_registers {recorder_qsys:inst2|ip_sata:ip_sata_0|block_sata_core_gxb:block_sata_core_gxb_inst1|SATA_CONTR:inst46|SATA_PHY:inst14|TX_BUS_MUX_SATA:inst1|inst6}]
create_generated_clock -name RX_SATA_CLK -source [get_pins {inst2|ip_sata_0|block_sata_core_gxb_inst1|inst2|ALTGX_SATA_alt4gxb_component|receive_pcs0|clkout}] -divide_by 2 [get_registers {recorder_qsys:inst2|ip_sata:ip_sata_0|block_sata_core_gxb:block_sata_core_gxb_inst1|SATA_CONTR:inst46|SATA_PHY:inst14|BUS_Former:inst9|tfDIVIDER}]

set_clock_groups -exclusive -group {SATA_CLK}
set_clock_groups -exclusive -group {RX_SATA_CLK}

  
# set_clock_groups -exclusive -group [get_clocks {blk_prim_pll|altpll_component|auto_generated|pll1|clk[2]}] 
# set_clock_groups -exclusive -group [get_clocks {inst2|ddr_1|recorder_qsys_DDR_1_controller_phy_inst|recorder_qsys_DDR_1_phy_inst|recorder_qsys_DDR_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]
